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Altera_Forum
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12 years ago

Use slow asynchronous modul in a fast synchronous mealy state machine cause timing er

Hello everyone, how can i use a slow asynchronous modul to calculate signals in one state of a fast synchronous mealy state machine without the Error Timing requirements not met? I tried to use...
Altera_Forum's avatar
Altera_Forum
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12 years ago

A clock enable signal doesn't change the requirements for timing closure. If the clock enable signal creates multi-cycle transfers, you have to specify them explicitely.