Altera_ForumHonored Contributor10 years agoUse of buffered and unbuffered clocks in circuit I was examining the postfit results of my design and noticed that the fitter automatically inserted CLKCTRL cells into several of the clocks in my design. That is well and good but I noticed that in...Show More
Altera_ForumHonored Contributor10 years agoI bet he has gated clock. I will put my throat for the bet.
Recent Discussionstiming violation fixIssues with downloadingQuartus Prime Lite 25.1 License Error - "Unable to checkout a license" (SALT_LICENSE_SERVER)Quartus Prime Pro 26.1 - Where to find Documentation of new Signaltap featuresError (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10