Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHere's an idea. Open your top-level file and go to File -> Create Symbol for it. Then create a new .bdf and insert that symbol into it. Right-click on the symbol and Insert Pins(or whatever the name is to add ports to every I/O of a block). You now have a top-level file that does nothing but wrap your design. Run Analysis & Elaboration, and create a partition on that first level(what was your top-level). Now try the same flow, but you're no longer exporting the top-level, just the level below it.
To be honest, I'm not a huge fan of this flow as I think it opens you up to issues if you have complicated I/O, like a DDR2 structure or something. There's a decent chance it will work, but not positive. Another possibility is to create a lower-level partition on the hierarchy/s that always have the critical paths, if your design is one that acts that way. Then just export that one, import into Q9.0, and at least you're rerunning the analysis on that portion. Of course, if you're using a beta version, I don't know if you can really be sure the timing models are final.