Forum Discussion
Fromhell777
New Contributor
5 years agoUse correct latch timing during place and route optimisation
As I understood the timing analyser treats level-sensitive latches similar to registers. When looking into the documentation the only option that you can execute to have a correct timing analysis of ...
KennyT_altera
Super Contributor
5 years agoIs that fine that you attached the design.qar for us to investigate?
Let's us know if you want to send the design.qar privately to Intel, I will arrange for that.
Fromhell777
New Contributor
5 years agoI cannot share my files due to confidentiality