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Honored Contributoruse an entity in process
I write four VHDL file
1) 1 bit full adder 2) 8 bit full adder 3) 1 bit flip flop 4) accumulator 1 and 2 and 3 is correct and I tested those , but I have a really big problem in accumulator! this is picture of accumulator that I want build by 1,2 and 3 : http://www.alteraforum.com/forum/attachment.php?attachmentid=10883&stc=1 I'm new in VHTL . I try to write a accumulator but it's full of error and logical problems. you can see for above code blow : 1) 1 bit full adder Library ieee; Use ieee.std_logic_1164.all; --------------------------------------------------------------------------- Entity fullAdder is port( Cin : in std_logic; x : in std_logic; y : in std_logic; s : out std_logic; Cout : out std_logic ); end fullAdder; Architecture fullAdder_logic of fullAdder is begin s <= x xor y xor Cin; Cout <= (x and y) or (x and Cin) or (y and Cin); end Architecture; 2) eight bit adder Library ieee; Use ieee.std_logic_1164.all; Use work.all; --------------------------------------------------------------------------- Entity eightBitAdder is port( Cin : in std_logic; x : in std_logic_vector(7 downto 0); y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); Cout: out std_logic ); end eightBitAdder; Architecture eightBitAdder_logic of eightBitAdder is component fullAdder port( Cin,x,y : in std_logic; s,Cout : out std_logic ); end component; signal carry : std_logic_vector(8 downto 0); begin carry(0) <= Cin; gen_add: for i in 0 to 7 generate lebel_fulladd: fullAdder port map (carry(i), x(i), y(i), s(i), carry(i + 1)); end generate gen_add; Cout <= carry(8); end Architecture; 3 ) 1 bit d_ff library ieee; use ieee.std_logic_1164.all; entity D_ff is port ( D: in std_logic; CLK: in std_logic; RST: in std_logic; Q: out std_logic ); end D_ff; architecture D_ff_logic of D_ff is signal ff_state: std_logic; -- This will hold flip flop state begin process(CLK) begin if rising_edge(CLK) then if RST='1' then ff_state <= '0'; -- Reset, change state to 0. else ff_state <= D; -- 'clock' in input. end if; end if; end process; -- Output current flip flop state Q <= ff_state; end architecture; 4) accumulator !! library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity accumulator is port ( Input: in std_logic_vector(7 downto 0); CLK: in std_logic; Output: out std_logic_vector(7 downto 0) ); end entity accumulator; architecture accumulator_logic of accumulator is component D_ff is port ( D: in std_logic; CLK: in std_logic; RST: in std_logic; Q: out std_logic ); end component; component eightBitAdder is port( Cin : in std_logic; x : in std_logic_vector(7 downto 0); y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); Cout: out std_logic ); end component; signal DFF_AC: std_logic_vector(7 downto 0); signal overFlow: std_logic; signal cout: std_logic; begin DFF_Ac0: D_ff port map ( '0', CLK, '1', DFF_AC(0)); DFF_Ac1: D_ff port map ( '0', CLK, '1', DFF_AC(1)); DFF_Ac2: D_ff port map ( '0', CLK, '1', DFF_AC(2)); DFF_Ac3: D_ff port map ( '0', CLK, '1', DFF_AC(3)); DFF_Ac4: D_ff port map ( '0', CLK, '1', DFF_AC(4)); DFF_Ac5: D_ff port map ( '0', CLK, '1', DFF_AC(5)); DFF_Ac6: D_ff port map ( '0', CLK, '1', DFF_AC(6)); DFF_Ac7: D_ff port map ( '0', CLK, '1', DFF_AC(7)); process(CLK) begin if rising_edge(CLK) then if overFlow = '0' then DFF0: D_ff port map ( DFF_AC(0), CLK, '0', DFF_AC(0)); DFF1: D_ff port map ( DFF_AC(1), CLK, '0', DFF_AC(1)); DFF2: D_ff port map ( DFF_AC(2), CLK, '0', DFF_AC(2)); DFF3: D_ff port map ( DFF_AC(3), CLK, '0', DFF_AC(3)); DFF4: D_ff port map ( DFF_AC(4), CLK, '0', DFF_AC(4)); DFF5: D_ff port map ( DFF_AC(5), CLK, '0', DFF_AC(5)); DFF6: D_ff port map ( DFF_AC(6), CLK, '0', DFF_AC(6)); DFF7: D_ff port map ( DFF_AC(7), CLK, '0', DFF_AC(7)); adder: eightBitAdder( '0', std_logic_vector(Input), std_logic_vector(DFF_AC), std_logic_vector(DFF_AC),cout); overFlow <= cout xor DFF_AC(7); end if; end if; end process; -- Assign output --DOUT <= our_ffs; end architecture; i can't fix this with out help!
