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Altera_Forum
Honored Contributor
11 years agouse an entity in process
I write four VHDL file 1) 1 bit full adder 2) 8 bit full adder 3) 1 bit flip flop 4) accumulator 1 and 2 and 3 is correct and I tested those , but I have a really big problem in accu...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Your post doesnt make a lot of sense. Have you got a testbench? can you debug this yourself? --- Quote End --- above code compile correctly , But when I simulate it functionality , it's diagram have a little bit wrong! I review code many time but I did not find where I do mistake . I take this picture from accumulator wave form : http://s6.picofile.com/file/8200419576/pic5.png It is right 60% but I don't know where I do mistake because I'm very very beginner.