Forum Discussion

BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Usage of negative edge trigger for dual clock RAM

Dear all, Greetings of the Day! We are having one dual port RAM with separate clock for port A and Port B. Port B related signals are driven within FPGA. While port A related signals will be driven...
Hdl
Timing
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


Thank you for using Intel Communities.


I have tried your original proposed design on Quartus 22.1std. Here are my answers to your questions:


1) Would Quartus be happy to implement this and infer memory block for this?

  • Yes, the RAM is inferred when I tried this.


2) Can this have any impact on achieving timing requirements for port A?

  • Let me check with my team first and get back to you on this.


Regards,

Nurina