Honored Contributor
Honored Contributorthank you for your reply. i cant remember the error message but i was about time delay of carying signal from out of one MF to input of another MF. well, i have done some optimizations on my vhdl codes to process some calculations in parallel. my study is working fine now. but i want to increase my vhdl programming technique. but i could not explain my question quitely, since i'm a beginner. i will try to ask in a different way:
consider you have to solve so many calculations and FPGA resources such as logical elements and embedded multipliers are limitted. therefore you have to use several altfp_mult for all multiplying process, several altfp_add_sub for all adding process etc. in a sequential structure. So how you code in vhdl to implement? What is the best or the most sutiable method for this type implementation? Could you please give me an example code or advise a tutorial or .....? Regards Bedri
