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Altera_Forum's avatar
Altera_Forum
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11 years ago

Upsampling QPSK Symbols

I am trying to implement QPSK modulator in FPGA using Verilog.

I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1

I channel will be: 1 1 0 0 and Q channel will be: 0 1 1 1

Now I need to upsample these two channels, assume I want to upsample by 8, does it mean that I change the "width" of each bit to 8? i.e. I channel will be: 00000001 00000001 00000000 00000000 and Q channel will be: 00000000 00000001 00000001 00000001

Or I just repeat each bit 8 time? i.e. I channel: 11111111 11111111 00000000 00000000 and Q channel: 00000000 11111111 11111111 11111111

After using the correct way of upsampling, how do I map ones and zeros to 1 and -1?

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks Kaz.

    How could you tell that Fc implies upsampling by 2?

    So all I have to do is to design the filter in MATLAB, calculate coeffs and feed them to FIR compiler.

    PS: In your previous reply when you gave example about DAC resolution, have not you should say: coeffs = round(2023* coeffs/max(coeffs)); as the DAC has 11 bits?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    11 bits signed (dynamic range = +/- 1023), one bit is sign bit

    rectangular symbols contain infinite frequencies. You plan to pass minimum bandwidth without losing information.

    The rule of not losing information is that you pass a bandwidth from 0 to half Rs (symbol rate).

    Your Fs to begin with is = Rs so you need to pass 0.5 Fs bandwidth

    Then you require minimum upsampling of 2 thus your filter will have to work at 2 *Rs speed and cutoff at same point of 0.5 Rs

    in other words if Fs is 1 then Fc becomes 1/4 (= 2/0.5)
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    OMG!! Thanks a Million Kaz!!! I got it now!

    I hope someday I will get quarter of your expertise :D

    Thanks again... I appreciate your help.