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Altera_Forum
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11 years ago

Upsampling QPSK Symbols

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel will be: 1 1 0 0 and Q channel ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks Kaz.

How could you tell that Fc implies upsampling by 2?

So all I have to do is to design the filter in MATLAB, calculate coeffs and feed them to FIR compiler.

PS: In your previous reply when you gave example about DAC resolution, have not you should say: coeffs = round(2023* coeffs/max(coeffs)); as the DAC has 11 bits?