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Altera_Forum
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11 years ago

Upsampling QPSK Symbols

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel will be: 1 1 0 0 and Q channel ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

That sounds brilliant! Can you please provide me with a quick example of scaling coeffs to DAC resolution?

Now just to make sure that I understand the other method (not using a single filter to do it all), I am going to describe how it should be and you tell me if I am right or wrong.

Taking the diagram I attached as a reference:

1- Mapping block will map I/Q to 1 and -1. (If I'm right, how wide this should be?)

2- I think after this stage I need to up-sample by 8 or so. (To the best of my knowledge, this is slightly different from interpolating which invloves filtering)

3- RRC filter will change the shape of the square samples to something more curved. (I don't know it is going to increase the sample rate, i.e. upsample)

4- Interpolate by upsampling (inserting zeros) and filtering, to accomodate mixer rate.

5- Finally upconvert to RF using mixers.