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Altera_Forum
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11 years ago

Upsampling QPSK Symbols

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel will be: 1 1 0 0 and Q channel ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I appreciate your help, thanks a lot. Actually yes I am still confused so I hope you answer my questions :)

I want to design the whole system in FPGA, so my DAC will produce the RF signal. I have already done FM modulation and now I am working to implement QPSK.

1- I still can't understand why do I need to scale I/Q to DAC resolution? (By the way, does the +1000 represent a DAC resolution in your example?) After mapping I/Q I will multiply them with carriers then sum both arms (I/Q channels) then send the modulated carriers to DAC (Digitally speaking), I think here lies my confusion with what you suggested in the first point in the previous reply.

2- Do you recommend using RRC to handle all of that? I have made a literature review and come out with the attached block diagram.