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Altera_Forum
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11 years ago

Upsampling QPSK Symbols

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel will be: 1 1 0 0 and Q channel ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You need to map I and Q raw binary values to constellation signal levels (of your system, DAC). That depends on your mapping to constellations.

e.g. if IQ pair is 00 is in first quadrant then map to I => +1000, Q => +1000

Then you apply upsampling using filter on the mapped values (raw data gone now).

In some cases, both mapping and upsampling (and possibly shaping) is done internally in the filter which will use raw binary values as inputs.