Uploading FPGA configuration

I am wondering if we can read Jic file from EPCS flash devices

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Ok, that's good to know. I use the JAM STAPL player verification option to confirm that EPC2 EEPROMs have been loaded with the .pof I expect.

Arguably, there's no need. If the FPGA is configured from a device loaded with a .pof, and you can confirm that .pof is correct, then the loaded FPGA will also be correct. The .sof is just another version of the .pof, but used by JTAG download.

If you're worried about a production board being loaded with the wrong configuration, then you should really have software read a hardware register. For example, I'll often have board ID, design ID, version, and timestamp registers. I also use pull-ups/downs on external pins to indicate a board revision. That way each .sof can enable functionality once they check they are loaded into the correct hardware.

If you have a bad JTAG connection, and your .sof download gets corrupted, then the FPGA will detect the error and drive the nSTATUS configuration pin low to indicate failure.

Cheers,

Dave

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