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I experimented a bit, it is possible to upload the .pof file from the FPGA using the Examine feature in the Quartus II Programmer. This works perfectly, to compare the downloaded and uploaded .pof files.
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Ok, that's good to know. I use the JAM STAPL player verification option to confirm that EPC2 EEPROMs have been loaded with the .pof I expect.
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But there seems to be no way to upload the .sof file.
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Arguably, there's no need. If the FPGA is configured from a device loaded with a .pof, and you can confirm that .pof is correct, then the loaded FPGA will also be correct. The .sof is just another version of the .pof, but used by JTAG download.
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I'm most interested in verifying if the correct files were programmed in, not the status of the FPGA after programming.
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If you're worried about a production board being loaded with the wrong configuration, then you should really have software read a hardware register. For example, I'll often have board ID, design ID, version, and timestamp registers. I also use pull-ups/downs on external pins to indicate a board revision. That way each .sof can enable functionality once they check they are loaded into the correct hardware.
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"The .sof will fail to configure the device if there was an error. -- Dave" : Do you mean if there was an error in the FPGA loading the .sof file then there would be an expected configuration error?
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If you have a bad JTAG connection, and your .sof download gets corrupted, then the FPGA will detect the error and drive the nSTATUS configuration pin low to indicate failure.
Cheers,
Dave
Honored Contributor
