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So lets say we have 64 DFFs (as in picture attached) each requiring a clk, rst and enable in parallel. I guess that's quite a lot of driving current needed right?
1. how do i measure the actual driving current needed?
2. is it good practice to connect all 64 (clk, rst and ena) together in parallel like in the picture, and drive them from just one input?
3. say clk is driven internally from a PLL, can the PLL drive all those FF? can it supply enough current to all? Or is there a limit some where in a datasheet?
4. say rst is driven from an external pin, can this pin handle the current needed?
5. transient currents create a lot of noise...
6. are there any fanout techniques used internally in the FPGA to split signals, like clk, rst and ena, in this case, to say groups of 8?
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Your electrical question was answered, but not the others.
1: Powerplay power analyzer, as mentioned.
2: There is no issue with driving all 64 locations as long as the design meets timing.
3: Yes, the PLL can drive all of them, either using local routing or global routing. As mentioned, you don't have to worry about current.
4: Same answer.
5: In the past, simultaneous switching noise, large numbers of physically close I/O pins switching levels simultaneously, could affect pins that weren't switching, potentially glitching the pins not switching. This could still be an issue with older devices, but most newer ones don't have a problem with it (the SSN analysis tool was removed from the Quartus software a while ago).
6: Absolutely. This is usually necessary for high fanout timing issues (so much fanout that destination logic needs to be placed further and further from the source, causing setup timing issues). The main recommendation is to perform register duplication directly in your HDL code. This gives you the most control. However, Quartus does include a max fanout constraint and a register duplication constraint you can use in the Assignment Editor to do this without altering your code.
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