up counter needs fixing - confused . simple question

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Also one more thing, in the picture I attached the Load input is driving multiple multiplexers. Is there a trick behind the scenes that takes care of the driving capabilities inside the FPGA. As in can one input drive all that logic at one internally? (is my question clear here?)

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It is driving muxes because altera registers do not have synchronous inputs, other than D. So synchronous set/reset have to be emulated with logic - hence the muxes.

Im not exactly sure what your question means - but assuming the design meets timing then this is pretty standard behaviour..