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I hope this can be helpful.
(Notice: I wrote the code but I didn't tested it, so take it only as an example...)
entity udcounter is
generic ( WIDTH : integer := 8);
port (CLK, UP, DOWN, RESET : in std_logic;
Q : out unsigned(WIDTH-1 downto 0) );
end entity udcounter;
architecture udcounter_a of udcounter is
signal cnt : unsigned(WIDTH-1 downto 0);
signal up1, dw1 : std_logic;
begin
process(RESET, CLK)
begin
if RESET = '1' then
cnt <= (others => '0');
elsif rising_edge(CLK) then
if (UP='1' and up1='0' and DOWN='0') then
cnt <= cnt + 1;
elsif (DOWN='1' and dw1='0' and UP='0') then
cnt <= cnt - 1;
--else leave cnt unchanged
end if;
up1 <= UP;
dw1 <= DOWN;
end if;
end process;
Q <= cnt;
end architecture udcounter_a;
PS for Tricky
Thank you for your remark. I agree what you say, but I couldn't make otherwise.
If I remove one or either I get an error like "unsigned is undefined"
What is the problem?
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Hey SEILASER, thank you very much. i just had to edit my code by adding few lines from your code and it worked. Thank you....:D
In your designs, dont you maybe have a design code to display graph on the vga monitor??
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