Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe problem is with these lines:
IF (PUSH_BUTTON_1'EVENT AND PUSH_BUTTON_1 ='0') THEN
ELSIF (PUSH_BUTTON_2'EVENT AND PUSH_BUTTON_2 ='0') THEN
What you've asked for is the falling edge of the buttons, but that format assume's it is a clock, and because you have used "elsif" you're trying to clock 1 register from 2 different clocks, which you cant do in an FPGA. The recommended sollution would be to provide a single clock that samples the button every clock cycle and comapre the registered version to the current state - that can tell you if you have a rising or fallinge edge of a button press. PS. SEILASER? you shouldnt use std_logic_unsigned and numeric_std in the same file.