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Altera_Forum
Honored Contributor
15 years agoI simply copy and paste this from one of my designs...
You need minor changes to manage up and down clocks instead of mine, which increments only. library altera; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.numeric_std.all; -- for the unsigned type entity mycounter is generic ( WIDTH : integer := 8); port (CLK, RESET, LOAD : in std_logic; DATA : in unsigned(WIDTH-1 downto 0); Q : out unsigned(WIDTH-1 downto 0) ); end entity mycounter; architecture mycounter_a of mycounter is signal cnt : unsigned(WIDTH-1 downto 0); begin process(RESET, CLK) begin if RESET = '1' then cnt <= (others => '0'); elsif rising_edge(CLK) then if LOAD = '1' then cnt <= DATA; else cnt <= cnt + 1; end if; end if; end process; Q <= cnt; end architecture mycounter_a; Regards Cris