Honored ContributorMy FIR is now working so far - thanks to Altera Guru "MSchmitt" - but I still have two problems left. Please have a look at the attached pictures - there is an unwanted offset attenuation of 6dB in the filter characteristic. What can I do against that?
Honored ContributorI'm using the following:
* DSP Development Kit Stratix III Edition EP3SL150N * HSMC Card with two ADC 14bit and two DAC 14bit * Quartus 8.0 mit SP1 (subscription edition) * mini circuits SLP-50+ alias filter The design file is attached ...Honored ContributorThe HSMC ADDA card has AC(transformer)-coupled in- and outputs, so it's clear that a possible DC bias does show at the output.
The ADC and DAC data representation is unsigned, to process the data without conversion, it's O.K to set the FIR data format to unsigned, as you did. If simulation/SignalTap waveform formats are also set to unsigned, the signal should show centered. The unsigned data representation is only applicable for a low-pass, it wouldn't work for a high-pass or bandpass filter. Personally I prefer a signed representation for digital signal processing. In this case, the ADC data has to be changed from unsigned (offset binary) to signed (two's complement) by inverting the MSB. The discussed 6 dB attenuation may be caused by the signal scaling of the ADDA board, but I'm not sure about.Honored ContributorSo, as you say - it should show up centered, but it doesn't ... any idea why?
I do not understand why an unsigned input data works only for lowpasses and not for high- or bandpasses. Can you write some words? I will try now to use a signed representation and post the outcome afterwards.Honored ContributorI don't know why the signal doesn't show centered. Tracing the signal through the design by simulator or SignalTap should clarify.
I must admit, that I'm not using the FIR compiler for filter design yet, so I'm not aware of it's specific operation or possible issues. Only a lowpass will transmit the input signals DC bias. Assuming the input signal is biased to midscale, it's surely the case for the said ADDA board. A lowpass keeps this property, a bandpass or highpass will have zero output bias, unless you apply an artificial offset. (I don't assume that the FIR compiler does for unsigned designs). When changing the filter design to signed (my preferred representation for DSP), you have to change the AD data from offset binary to two's complement by inverting the MSB, and vis-versa for the DA output.Honored ContributorBecause the FIR output looks correct (except for a possible offset), it seems clear that the above internal signal has a wrong display format.
The reason for the apparent offset is still unclear to me. Would you mind to post a quartus archive (*.qar file) of the full test design, including filter parameters and signal tap definition?Honored ContributorNo problem :D.
Honored ContributorI see, that the original (unsigned) filter design implements a DC gain of 0.57 (sum of integer coefficients = 1167, scaling factor = 2048). This is, what you see as an offset in the unsigned SignalTap. The input data is centered to midscale (8192), the output data to about 4650.
If you use signed data representation throughout the design, the data should stay zero biased when passing the filter, but still attenuate the signal level. The arbitrary gain is apparently a result of the FIR compiler's scaling method, depending on the number of coefficients.Honored ContributorI thought I was using only signed representations, when switching the pulldown in the FIR comiler to "signed" - so, this is obviously not the case - what do I have to do in addition?
:confused::confused::confused: So, if the arbitrary gain is a result of the number of coefficients - what number would you suggest to get optimal results? Would it be a good idea to switch from "auto scaling" maybe to e.g. "auto scaling to power 2"? Under what conditions?Honored ContributorI basically wanted to report, that the attenuation is introduced by the FIR compiler. I didn't check the options to change this behaviour, it should be discussed in the FIR compiler manual. As I said, I don't use the tool in my designs yet. But I expect, that you can basically achieve a gain of 1.
I also didn't check the implications of using different number represenation with the FIR tool. I just told, how it should be according to usual DSP practice. Apparently, the ADC number format can be switched in your ADDA hardware, otherwise the MSB has to be inverted, most likely necessary for the DAC.Honored ContributorI'm not an expert but wonder if you are able to simulate your digital filter behaviour.
If running a simulation with a constant input, you see it lowered, then it depends on the FIR filter. Further the simulation can tell you which is the correct format of the output (MSB representation etc.) Otherwise, can it be the DAC? hope this helps.
