Unroll VHDL records using Modelsim/TCL

Just wonder how to examine all subelements of a VHDL record when I don't know the attribute names.

One could parse the output of describe <signal_name> to get the attribute names but maybe there is a better way.

In the end I want to have a list of all primitive signals (eg. STD_LOGIC, STD_LOGIC_VECTOR) contained in the record.

I'd like to do this for a fault injection campaign.