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Altera_Forum's avatar
Altera_Forum
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9 years ago

University VWF fault

Good afternoon,

I was wondering if anyone could possibly offer me some help, as a mature student going back to study EE after a 20 year break I'm finding some things a little testing, I have been asked to design a matrix multiplier, I have done this by creating a chip with 3 multis and adders, when compiled it works produces a VWF, when I put 9 chips together and compile all is good but when I try to produce a VWF all I get is this message

Top level modules:# multiplxer

# End time: 16:36:55 on Apr 19,2017, Elapsed time: 0:00:04

# Errors: 0, Warnings: 0

# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014

# Start time: 16:36:56 on Apr 19,2017

# vlog -work work Waveform2.vwf.vt

# -- Compiling module multiplxer_vlg_sample_tst

# ** Error: Waveform2.vwf.vt(31): near "0": syntax error, unexpected INTEGER NUMBER, expecting ')'

# End time: 16:36:56 on Apr 19,2017, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

# ** Error: C:/altera/15.0/modelsim_ae/win32aloem/vlog failed.

# Executing ONERROR command at macro ./multiplxer.do line 4

Error.

any help would be gratefully received

cheers Boots

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    There is an error in your code, which we can't see. Attach some code to the post for us to look at.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    thank you for the reply Alex, a daft question but where would i find the code?

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Did you not write it? Is your design captured using a Quartus' schematic?

    Attach 'Waveform2.vwf.vt' for starters.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    my design was built using quartus schematic, i couldnt load the file so had to zip it and then load it, thanks for taking the time to help me with this issue

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    All of your signal names start with a number. In verilog (and VHDL), all identifiers must start with an alphabetic character (a-z, A-Z) or an underscore _. It cannot start with a numeric character.

    Its annoying, because schematics allow you name name everything with a number (0-9). But this will then not work when you try and simulate it.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Team,

    Thank you so much for the guidance, it turned out it was the naming of my signals, changed them to start with an under score and boosh sorted, waveform produced and correct

    thanks again Paul