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Altera_Forum
Honored Contributor
Honored ContributorUniversity VWF fault
Good afternoon, I was wondering if anyone could possibly offer me some help, as a mature student going back to study EE after a 20 year break I'm finding some things a little testing, I have been ...
Altera_ForumHonored Contributor
Honored ContributorAll of your signal names start with a number. In verilog (and VHDL), all identifiers must start with an alphabetic character (a-z, A-Z) or an underscore _. It cannot start with a numeric character.
Its annoying, because schematics allow you name name everything with a number (0-9). But this will then not work when you try and simulate it.
