Uniphy Platform Designer Error: "Cannot find sequencer/sequencer.elf"
Prior to Quartus Prime Std v19, Intel used Cygwin for the Nios II Command Shell. Version 19.1 and beyond, they switched to using Ubunto 18.04 TLS and Windows Subsystem for Linux (WSL) to operate the Nios Command Shell. Here's a quote from the following support article.
https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.html
"Starting with the Nios® II EDS in the Intel® Quartus® Prime Pro Edition software version 19.2 and Intel® Quartus® Prime Standard Edition software version 19.1, the Cygwin component in the Windows* version of Nios II EDS has been removed and replaced with WSL."
I've been unable to compile Platform Designer projects that use a UniPhy memory controller starting with Quartus Prime Std version 19.1 due to the errors mentioned below. Consequently, I've had to keep the revision locked at version 18. It is time to resolve the problem with later versions as my IP is becoming outdated.
This same issue is already mentioned (but not resolved) several times, starting with version 19 and subsequent releases. I am currently running Quartus Prime Std 21.1.0.842.
Here’s a few of the times it is mentioned:
Here is how the error/issue shows up in Platform Designer:
I’ve deleted all prior versions of Quartus in hopes that would clear up the issue…it didn’t.
- I’m able to successfully run Nios II Command Shell, which validates that I’ve successfully installed Ubunto 18.04 TLS and WLS.
- I’ve set WLS version to ‘1’
- I’ve installed the following packages:
- sudo apt update
- sudo apt upgrade
- sudo apt install wsl
- sudo apt install dos2unix
- sudo apt install make
- I’ve confirmed the appropriate system environment variables:
- QUARTUS_ROOTDIR E:\intelFPGA\21.1\quartus
- QSYS_ROOTDIR E:\intelFPGA\21.1\quartus\sopc_builder\bin
- SOPC_KIT_NIOS2 E:\intelFPGA\21.1\nios2eds
From what I read, it has never been successfully resolved. I am VERY surprised that Intel has not taken the time to come up with a clear resolution to it. I certainly can’t be the only one out there that is attempting to compile a Platform Designer project with a UniPhy DDR3 memory controller.
I am absolutely stuck at this point. Any guidance would be most appreciated.