Uniphy DDR3 Controller has no afi_half_clk

Question

I have instantiated a (soft) DDR3 controller for the MAX10 (Altera MAX10 FPGA Development Kit) with a half rate interface.  The controller produces an afi_clk, but no afi_half_clk.  I'm using Quartus 16.1 Prime Lite.  It appears there was a problem with this in Quartus 12, but it is said to have been fixed.

altera_forum · Answer

Hi,

For Max10 DDR3, the afi_clk itself is already a half rate clk which is 150MHz. You shouldn't compare Max10 with older product family architecture.

Feel free to checkout Max 10 device EMIF user guide doc.

https://www.altera.com/documentation/sam1396240992710.html

Thanks.

Regards,

spdl2001

(This message was posted on behalf of Intel Corporation)

altera_forum · Answer

Thanks, I eventually figured that out.  Good to have confirmation.

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Uniphy DDR3 Controller has no afi_half_clk

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