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Altera_Forum
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8 years ago

Uniphy DDR3 Controller has no afi_half_clk

I have instantiated a (soft) DDR3 controller for the MAX10 (Altera MAX10 FPGA Development Kit) with a half rate interface. The controller produces an afi_clk, but no afi_half_clk. I'm using Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

For Max10 DDR3, the afi_clk itself is already a half rate clk which is 150MHz. You shouldn't compare Max10 with older product family architecture.

Feel free to checkout Max 10 device EMIF user guide doc.

https://www.altera.com/documentation/sam1396240992710.html

Thanks.

Regards,

spdl2001

(This message was posted on behalf of Intel Corporation)