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Altera_Forum
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9 years ago

Uniphy DDR3 Controller has no afi_half_clk

I have instantiated a (soft) DDR3 controller for the MAX10 (Altera MAX10 FPGA Development Kit) with a half rate interface. The controller produces an afi_clk, but no afi_half_clk. I'm using Quartus...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks, I eventually figured that out. Good to have confirmation.