UniPHY DDR3 Controller Fitter error

My software is Quartus II 14.0.0 Build 200 07/17/2014 Full version(University program).

I have DE5 board, it is 2 SODIMM-DDR3 module.

so I make 2 SODIMM-DDR3 project(Use PLL Slave UniPHY-A, PLL Master UniPHY-B).

this project reference from DE5 sample project(C:\Terasic\DE5-Net_Install\Demonstrations\DDR3x2_Test).

but, i can't compile complete. it have errors.

Error (175020): Illegal constraint of pin that is part of RAM: 1-PORT <project_top> to the region (189, 129) to (191, 129): no valid locations in region

Info (14596): Information about the failing component:

Info (175028): The pin name: DDR3B_DM[6]

Info (14597): No legal location could be found for this component out of 1 considered location(s). Reasons why each location could not be used are summarized below:

Info (175015): The I/O pad DDR3B_DM[6] is constrained to the location PIN_H15 due to: User Location Constraints (PIN_H15)

Info (14709): The constrained I/O pad is contained within this pin

Error (175006): Could not find path between source fractional PLL and the pin

Info (175026): Source: fractional PLL <project_top>:top|ddr3_b:DDR3B|ddr3_b_0002:ddr3_b_inst|ddr3_b_pll0:pll0|pll1~FRACTIONAL_PLL

Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X0_Y1_N0

Error (175022): The pin could not be placed in any location to satisfy its connectivity requirements

Info (175029): 1 location affected

Info (175029): H15

It is not possible such errors to resolve come out more.

I try execute TCL ddr3_a_p0_pin_assignments.tcl and ddr3_b_p0_pin_assignments.tcl

but still this errors.

Please help me.