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Altera_Forum
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16 years ago

Uninferred ram logic cyclone III

I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but a...
Altera_Forum's avatar
Altera_Forum
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16 years ago

No, it's not.

But Quartus, by default, does not use M9K blocks for such small memories. You can force it to, either by setting the "Allow Any RAM Size for Recognition" option (Analysis & Synthesis) or by specifying "M9K" as the ramstyle attribute.

That said, unless you're having trouble fitting your design or achieving timming closure, my advice is to let the tools figure it out automatically.