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Altera_Forum
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15 years ago

Uninferred ram logic cyclone III

I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi

is it neccesary that ram declaration(or deduction) neccessarily takes up full M9K block?

read in one of the posts that quartus can pack more than one ram declarations in a single M9k block. so "uninferred due to inappropriate RAM size" due to small memory size is a bit confusing.

Thanks and regards

sanat