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Altera_Forum
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15 years ago

Uninferred ram logic cyclone III

I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Use altsyncram, there is no MLAB in CIII

I think your memory is too small that is why it is using logic instead of block ram.

I used to have that issue, but it went away when I inferred a bigger RAM.