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Altera_Forum
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15 years ago

Uninferred ram logic cyclone III

I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

hi

my ram size is word length 7 bits and depth 16 words.

type MEM is array (0 to 15) of std_logic_vector(6 downto 0);

signal in_buf_length:MEM;

attribute ramstyle:string;

attribute ramstyle of in_buf_length:signal is "no_rw_check";

thats my ram definition template