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Altera_Forum
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15 years ago

Uninferred ram logic cyclone III

I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

cyclone III info dump says so

"Warning: Assertion warning: Device family Cyclone III does not have MLAB blocks -- using available memory blocks"

and uses altsyncram

what does Info: RAM logic "in_buf_length" is uninferred due to inappropriate RAM size imply ??

thanks and regards