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DongWang-BJTU's avatar
DongWang-BJTU
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Unexpected memory generated in Kernels by the OpenCL compiler

unexpected memory found in the final report of quartus as follow:

the entity (xxx_B11) consums 112 M20K memory blocks after P&R:

But in the report.html, there is no such memory usage:

I wonder why this memory is used and how can I avoid such things. Because it consume too much M20K resources.

4 Replies

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor

    Hello,

    Kindly allow me some time to investigate more about this case.

    I will reply to you once I get a feedback.

    Thanks

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor

    Hello,

    Can you share with me some information about your compilation? Like, which Quartus version did you use? which device?

    Sometimes, the compiler uses on-chip memory as part of optimization to enhance any loop or iterated process.

    thanks

    • DongWang-BJTU's avatar
      DongWang-BJTU
      Icon for Occasional Contributor rankOccasional Contributor

      Hi,

      I have tried v17.1 and v18.1, both has the same results. I am using the DE5-net board with an Stratix-V GXA7 FPGA on board.

      Can such opimization be controlled manually by using pragma or compilation options ?

      I did more experiments on different implementations with different resource utilization rates. It turns out that when the overal resource utilization of the implemented design is relative small, there will be no memory consumptions by these entities. Is it possible these memory blocks are generated during P&R by quartus rather than the opencl compiler ?

      If it is generated by the aoc compiler, the numbers should be collectable and reported in the report.html file.

  • DongWang-BJTU's avatar
    DongWang-BJTU
    Icon for Occasional Contributor rankOccasional Contributor

    Hi,

    I have tried v17.1 and v18.1, both has the same results. I am using the DE5-net board with an Stratix-V GXA7 FPGA on board.

    Can such opimization be controlled manually by using pragma or compilation options ?

    I did more experiments on different implementations with different resource utilization rates. It turns out that when the overal resource utilization of the implemented design is relative small, there will be no memory consumptions by these entities. Is it possible these memory blocks are generated during P&R by quartus rather than the opencl compiler ?

    If it is generated by the aoc compiler, the numbers should be collectable and reported in the report.html file.