Unexpected large routing delay on input ports

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I wonder if this going to be any good:

you set the coding to use one io register then assign it to A,B,C

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That is the problem - we cannot do this. The state machine acts as an avalono-mm interface, and it needs to response the input signal, let's say, wait_request within 1 cycle (or less) by deasserting the read/write signal and sampling the input data. If we use another level of register, the state machine cannot response in time.

Thanks.