Unexpected large routing delay on input ports

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Have you set synthesis tool to use io registers (e.g. through assignment editor) for relevant inputs?

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Thanks. We have enabled the fast input regs. However in our code, the input port actually drives three different register groups in the state machine, like

state 1: reg_A <= cpld_gpio [11];

state 2: reg_B <= cpld_gpio [11];

state 3: reg_C <= cpld_gpio [11];

In this case, even after enabling fast input regs, only one register group will be located next to the I/O port. The other two are still located in the core and have large delay.