Honored Contributor
Honored ContributorHi,
So how do we get rid of this altera jtag (USB Blaster) problem? I am using NEEK, Quartus II 10.0sp1 Web Version and was trying to do NiosII Hardware Development Tutorial. this is the .sdc# Update -period with clock period (in nanoseconds) of the clock driving the fpga create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] # Setting LED outputs as false path, since no timing requirement set_false_path -from * -to [get_ports LEDG [*]] # Constraining JTAG interface# TCK port create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# from altera knowledge support# create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}# Clock constraints# create_clock -name "MCLOCK" -period 20ns [get_ports {altera_reserved_tck}] -waveform {0.000ns 10.000ns}# Automatically calculate clock uncertainty to jitter and other effects.# derive_clock_uncertainty # cut all paths to and from tck set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]
