Understanding Recovery and Removal in TimeQuest

Hi Rysc,

Since I posted my thoughts I will try to remove some confusion.

Essentially it is the register setup/hold that is all there. Altera calls it micro

sometimes or reg Tsu/TH ...xilinx calls it reg Tsu/TH. I believe the term micro is very misleading.

Anyway, the central point in fulfilling timing is that the source of signals(D,clk) should not violate timing of destination register.

If the interest is at input registers then we are only intersted to know the reg Tsu/TH at pin perspective(what you call it macro...). The internal(micro or reg ...) are irrelevant practically here.

The relation is this:

Tsu(at pin) = reg Tsu + data delay -clk delay

TH(at pin) = reg TH -data delay + clk delay

i.e. the delays cause a shift of timing window but can't change its length

Thus you can have TH(at pin) zero or negative implying nothing more than

that data is forced a good delay by the time it reaches the register compared to clk.

Devices with zero or negative hold are very attractive because otherwise TH can be violated readily as data from source changes after launching edge by a whisker(1 or 2 ns).

The same applies internally but here instead of pins we have the source register responsible to fulfil timing of destination with respect to the next latching clk edge. It is the tool that looks after the values, not the field designer.

At the output register, the designer takes over but needs to know the Tsu/TH of extrnal device(at device pins or preferrabley at fpga pins) then controls Tco(or delays) at fpga.

Hope this is clear