Understanding Recovery and Removal in TimeQuest

To Malachite's question, you're absolutely right, and that's what gets taught in school. We tend to call that the micro-setup(uTsu) of the register, along with the other micro parameters(uTh, Tco). Those numbers all show up in TimeQuest's calculations.

The problem with them is they only specify that the latch register will fail(go metastable) if the data transitions in that tiny micro-setup/hold window. It's really not that useful information from a system perspective. (I see people do timing simulations and think it's also doing static timing analysis, where they don't realize that if the data is so late that it doesn't violate their uTsu/uTh of the register, then the data is just in the next window and the simulator will never issue a warning. Yes it's different functionality, but it really needs to be captured as an issue by static timing analysis).

Anyway, yes you're right, and now forget that definition. : )

From a system-level, a source register launches data, say at time 0ns, and the destination latches it, say at time 10ns. So for your system to operate, the data needs to get their in time to be successfully latched. This includes meeting the uTsu, it includes clock delays to both the source register and destination register(i.e. clock skew) and your data delay. In other words, the setup requirement is this macro-level view of the transfer, not a characteristic of the registers by themselves.