Understanding Recovery and Removal in TimeQuest

Hi all,

I just happened to read this doc. I appreciate Rysc's efforts to stimulate discussion in this area but it is far from clear and current consensus.

The central theme is very simple. every register specifies a timing window around its clk edge at which its input D must not change. This is common sense as the clk edge then wouldn't "see" what to read(read pre-edge or post edge state or end up in nonbinary state). The part before edge is setup time and that after is hold time. Setup or hold are no different in nature as they are just part of this timing window, however, avoiding their violation is as different as their relation to clk edge!

Another important part of our scenario is the source of signals. In RTL chain we need to control things from the source point. this could be the pins or the internal sourcing register. We need to know how the source "sees" setup/hold of destination register from its perspective and then using delays and knowing the fact that there is always finite source Tco, then timing of dest. register can be controlled.

In short:

setup is avoided by not exceeding fmax(in fact setup determines fmax).

hold is avoided by inserting a bit of delay on Q-D than that of clk or avoiding gated clocks.

I usually leave it to the tool but

user remedy for setup violation: pipeline more i.e. breakup logic into smaller clouds. reregistering is not efficient. or put less delay on Q-D or on reset.

user remedy for hold violation: insert more delay on Q-D or reset.

Sensible designers register the reset in its clock domain. This was discussed nicely and thoroughly in a previous thread.

It is also common to target zero or negative hold(source perspective).

Remember hold time is more vulnerable to violation as source data changes shortly after source clk edge(Tco)...

*if your clk is even few Hz, hold time violation can occur if not catered for.

but setup violation is impossible unless the flipflop is made in the kitchen