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Altera_Forum's avatar
Altera_Forum
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13 years ago

Undefined module: altera_pll was used

Hello,

I'm simulating a Quartus design in Active-HDL and I'm getting the following error:

Undefined module: altera_pll was used. Port connection rules will not be checked at such instantiations.

Where can the altera_pll simulation be found, so I can add it to the project?

Thanks,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    If you want to simulate your PLL you have to use the <pll_megacore_name>.vho or <pll_megacore_name>.vo file in the <pll_megacore_name>_sim directory and used the Altera library altera_lnsim.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hello,

    I also have a same problem. I've used .vo file and altera_lnsim.sv file. Then I've seen a message like below.

    # ** Warning: (vsim-3017) <work_area>/sim_PLL_ArriaV/RTL/ALT_PLL_CLK.vo(51): [TFMPC] - Too few port connections. Expected 25, found 5.

    ALT_PLL_CLK.vo is a generated file. I've checked altera_lnsim.sv file and there were 25 ports in the altera_pll

    module. But there are only 5 ports in altera_pll in ALT_PLL_CLK.vo.

    Could you tell me what is a problem?