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I am not able to increase fmax up to 120MHz.
But when i dont use constrains for input output, i achieve nearly 200MHz.
You can see my 2 designs. The differences are only in sdc file .... and the differences of fmax is massive.
How it is possible ? How can i increase fmax, when i use constrains to all inputs and outputs ?
Jan
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Running at 200MHz inside the FPGA does not matter if you cannot get signals in and out of the FPGA at that speed.
Set input and output delay is used to model the paths from the external driving device to the FPGA, and from the FPGA to whatever device it is driving. TimeQuest is telling you that at 200MHz, you will not be able to get the signals in and/or out of the FPGA.
Adding more pipe-lining may be one solution to use an extra clock cycle to fix this problem.
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