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New Contributor

2 years ago

Unconstrained paths of Generic Serial Flash Interface Intel FPGA IP

Hello I am using Arria 10 SX and I have in the QSYS Platform design the following IP: Generic Serial Flash Interface Intel FPGA IP After compilation finished I notice that in the Timing Analyzer – ...

hps_top_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_if_ctrl_1911_yehmafa.txt106 KB

Timing

HamzahS

New Contributor

1 year ago

Hello,

I'm facing the same issue and would like to kindly ask if the matter was resolved/answered.

Thanks

-Sulaiman

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Unconstrained paths of Generic Serial Flash Interface Intel FPGA IP

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