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Altera_Forum's avatar
Altera_Forum
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9 years ago

Unconstrained clock inside J2A Master?

For some reason, I'm getting this as an unconstrained clock inside the JTAG to Avalon master bridge I'm using in Qsys for System Console access:

u_flash_control|j2a_master|j2a_master|transacto|p2m|address[10]

Why would an address signal inside an IP be considered as an unconstrained base clock? It doesn't seem to affect my design.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    After running TimeQuest type:

    create_clock -name bad_clk {u_flash_control|j2a_master|j2a_master|transacto|p2 m|address[10]}

    report_timing -setup -npaths 10 -detail full_path -to_clock bad_clk -panel_name "-> bad_clk"

    report_timing -setup -npaths 10 -detail full_path -from_clock bad_clk -panel_name "bad_clk -> "

    If something gets reported, analyze how that address[10] is used as a clock in the Path details.