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Honored Contributor
Honored ContributorUnconnected CLK input to DFF defaulting to VCC with no warning (AHDL design)
I have just debugged an issue with an AHDL design where I had unintentionally not connected a CLK to a couple of DFF registers. Apparently Quartus synthesis does not give a warning and connects th...
Altera_ForumHonored Contributor
Honored ContributorI thought a DFF primative in AHDL required a CLK input so was surprised that tool defaults unconnected CLK input to 1 and compiles normally.
Yes I am still supporting some very old FPGA devices in legacy boards requiring Quartus 9 and using still AHDL in those cases. But going to VHDL on new designs.
