Forum Discussion
Altera_Forum
Honored Contributor
9 years agoUnable to synthesize the design with Macros and header files due to undefined Macros
Hi, I have a design with some Macros and these are being used in multiple files. These Macros are defined in the header file <Macro_defs>.vh. I have added the <Macro_defs>.vh file in my Quartus...
Altera_Forum
Honored Contributor
9 years agoI think you do need to specifically reference/include the info. It's my understanding that the scope of something included is dependent on the synthesis engine, and therefore risky. I believe the whole `include is being deprecated, or recommended not to be used, and packages should be recommended instead. For example, if you have a typedef, wrap it in a package in classes.sv:
package classes; typedef enum logic[4:0] { FIRMWARE, LOC_MMR, LOC_LA, ** LEG_IOH, IOAPIC,*******} t_class; endpackage : classes In the file that uses it, there no longer is a `include that has to point to the location of the file and is therefore dependent on directory structure. Instead just do: //No longer use this:`include ../somedir/librs/classes.sv import classes::* module lower ( input coreclk, input hemi_select, input kti_addr, input t_class bike, Now this file can be added anywhere and it doesn't have to maintain a pointer to the package, nor does it rely on whether the synthesis treats included info as global or not. (I'm somewhat new to this, so just passing along what I've heard...)