Forum Discussion
Loopback
New Contributor
2 years agoUnable to generate simulation files for avalon memory mapped read, write and slave IP
I have an existing QPP project, where I want to generate simulation files, so that I can better understand the inter module communication and data flow. I'm getting following errors in the generate d...
KennyT_altera
Super Contributor
2 years agoAs we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.