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Loopback
New Contributor
New ContributorUnable to generate simulation files for avalon memory mapped read, write and slave IP
I have an existing QPP project, where I want to generate simulation files, so that I can better understand the inter module communication and data flow. I'm getting following errors in the generate d...
LoopbackNew Contributor
New ContributorYes, this is in Platform Designer. When I open existing IP in Platform Designer, I go to Generate -> Generate HDL -> simulation model -> Verilog. When I go ahead, I get this error in the Generate dialog box saying, "Generate completed with errors and warnings".
