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Loopback's avatar
Loopback
Icon for New Contributor rankNew Contributor
2 years ago

Unable to generate simulation files for avalon memory mapped read, write and slave IP

I have an existing QPP project, where I want to generate simulation files, so that I can better understand the inter module communication and data flow. I'm getting following errors in the generate d...
Platform
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

What are these? Is this in Platform Designer? Where are you seeing these errors? What exact steps are you following? More details needed.